1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device including a plurality of memory cells.
2. Description of Related Art
A semiconductor device including a plurality of memory banks has been known (see JP8-221978A, JP2000-11647A, and JP2002-216480A). Each memory bank includes a plurality of memory cells that are arranged in a matrix manner.
Each memory cell includes a transistor and a capacitor. A gate of the transistor of each memory cell is connected to a word line. A source of the transistor of each memory cell is connected to the capacitor. A drain of the transistor of each memory cell is connected to a bit line. Each bit line is connected to a sense amplifier. In addition, a semiconductor device is provided with a data amplifier. The data amplifier amplifies write data, which is to be written into a memory cell, and read data that has been read from a memory cell. A Y-switch is provided between each sense amplifier and the data amplifier.
Each memory bank is connected to an XDEC (X-decoder) and a YDEC (Y-decoder). The XDEC selects a word line according to an X-address signal. The YDEC selects a Y-switch according to a Y-switch selection signal (hereinafter referred to as a “YS selection signal”) corresponding to a Y-address signal, and turns on the Y-switch that is selected.
When the YDEC selects a Y-switch and turns on the selected Y-switch, it means that the YDEC selects a sense amplifier connected with the turned-on Y-switch, and moreover that the YDEC selects a bit line connected with the sense amplifier.
The data amplifier connects to a memory cell, which is identified by the X-address signal and by the Y-address signal, through the Y-switch that is turned on by the YDEC and through the sense amplifier that is connected with the Y-switch.
The data amplifier receives a data amplifier control signal, and operates according to the data amplifier control signal.
For example, when the data amplifier receives a data amplifier control signal, which indicates a reading of data, and when the data amplifier connects to a memory cell, the data amplifier receives data written into the memory cell and amplifies the data (hereinafter referred to as “read data”).
Further, when the data amplifier receives a data amplifier control signal, which indicates writing of data, and data to be written (hereinafter referred to as “write data”) and when the data amplifier connects to a memory cell, the data amplifier amplifies the write data and outputs the write data that is amplified to a sense amplifier.
A semiconductor device (hereinafter referred to as a “divided memory semiconductor device”) is assumed in which a memory bank is divided into a plurality of memory areas, each memory area is provided with a YDEC, YDECs that are connected in series, a YS selection signal is supplied from an end of a series circuit composed of the YDECs, and each memory area is provided with a data amplifier.
The inventor has found that such a divided semiconductor device has a problem in which it is difficult to prevent an increase in circuit size.
The problem found by the inventors will be described below.
In the above described divided memory semiconductor device, a YS selection signal may degrade while passing through a YDEC which has first received the YS selection signal (hereinafter referred to as a “first YDEC”). The degradation of a YS selection signal can cause operational failure of a YDEC. To prevent degradation of the YS selection signal, a repeater may be provided between YDECs.
However, if a repeater is provided, a YS selection signal will be delayed by the repeater.
Accordingly, timing when a YDEC (hereinafter referred to as a “second YDEC”), which receives a YS selection signal through the first YDEC and through the repeater, turns on the Y-switch, that is, timing, when the second YDEC selects a sense amplifier, is delayed by a delay due to a repeater, from timing when a second YDEC selects a sense amplifier in a condition where there is no repeater.
Therefore, to make a timing to select a sense amplifier coincide with timing to input a data amplifier control signal into a data amplifier, timing to output the data amplifier control signal to a data amplifier, which is connected with the sense amplifier selected by the second YDEC, needs to be delayed by a delay caused when the second YDEC selects the sense amplifier, that is, a delay due to the repeater.
FIG. 1 is a diagram illustrating an example of output controller 101 which delays output timing of a data amplifier control signal. Output controller 101 shown in FIG. 1 is used in a semiconductor device including first and second memory areas into which a memory bank is divided in the wiring direction of a word line.
In FIG. 1, output controller 101 is connected to data amplifiers 102a and 102b. 
Data amplifier 102a is connected to a memory cell identified by an X-address signal and by a Y-address signal via a sense amplifier selected by a first YDEC. Data amplifier 102b is connected to a memory cell identified by an X-address signal and by a Y-address signal via a sense amplifier selected by a second YDEC.
Output controller 101 includes a plurality of D-latches 101a, a plurality of D-latches 101b, a plurality of AND gate circuits 101c, a plurality of AND gate circuits 101d, and a plurality of delay circuits 101e. 
Output controller 101 receives a data amplifier control signal “a” and a data amplifier control signal “b”. Such data amplifier control signals “a” and “b” are signals composed of a plurality of bits.
A data amplifier control signal “a” composed of a plurality of bits is latched by D-latches 101a in parallel at the rising edge timing of read/write clock RWCLK, and after that, when the read/write clock RWCLK is “H”, the data amplifier control signal “a” passes through AND gate circuits 101c and is outputted to data amplifier 102a in parallel.
A data amplifier control signal “b” composed of a plurality of bits is latched by D-latches 101b in parallel at the rising edge timing of the read/write clock RWCLK, and after that, when the read/write clock RWCLK is “H”, the data amplifier control signal “b” passes through AND gate circuits 101d. Then, each bit of the data amplifier control signal “b” is delayed in respective delay circuits 101e and outputted to data amplifier 102b in parallel. The amount of delay for delay circuits 101e is set to the amount of delay in the repeater.
In output controller 101, each bit of the data amplifier control signal “b” is delayed. Thereby, control timing of a data amplifier can be synchronized with timing to select a sense amplifier. Therefore, data reading and writing operations can be performed precisely.
However, in output controller 101, delay circuits 101e is provided for each bit of data amplifier control signal “b”, and accordingly, the number of the delay circuits is equal to the number of bits of the data amplifier control signal. Thus, the circuit size of the semiconductor device is increased.